The present invention relates generally to radio receivers in which intermediate frequency signals are processed digitally, and more specifically to an automatic gain control circuit that compensates for edit wideband signal power.
Modern radio receivers, such as used in cellular telephone, wireless Local Area Network (LAN), wireless Internet access systems, and similar equipment typically now employ digital signal processing techniques to some degree. Digital signal processing permits the replacement of physically large, costly, and unpredictable analog filtering components with their digital counterparts. These receiver architectures require high speed, wideband, analog-to-digital converts (ADCs) and digital filters. Present day ADC technology permits sampling at Intermediate Frequency (IF) or even greater frequency ranges. However, by replacing traditional analog filters with digital filters implemented after digitization, the ADC potentially also samples out-of-band unwanted signal components. These unwanted signal components may consist of adjacent channels, extra noise, or even jamming signals along with the desired signal of interest.
Direct application of analog receiver architectures to a digital implementation therefore, is often not sufficient to provide the required signal filtering properties. One difficulty stems from the fact that analog demodulation techniques are not directly adaptable to digital receivers. For example, clipping of a received signal lowers out the probability of correctly detecting the signal of interest and the data derived therefrom.
To reduce clipping, digital receivers often include one or more variable gain amplifiers that permit the gain of the receiver to be adjusted by a feedback control signal. The process of adjusting the received signal in this fashion is called Automatic Gain Control (AGC). In the typical digital receiver, the AGC circuitry measures an output signal power of the variable gain amplifier. This measured value is then compared with a value representing the desired signal power to derive an error signal. The error signal is then used to control the variable amplifier gain so that the output signal strength coincides with the desired output signal power. In the typical desired arrangement, the AGC circuit therefore may hold the amplitude of the output close to the full dynamic range of the analog-to-digital converter.
In the presence of out-of-band signal components, standard gain control loop architectures are often insignificant to guarantee proper analog-to-digital converter operation. Especially in the cellular environment, a digital receiver may receive signals that exhibit rapid and wide variation in signal power. For example, in Code Division Multiple Access (CDMA) mobile wireless communications, it is necessary to precisely control the power level of transmitted signals for proper capacity management.
Some have proposed the use of an AGC circuit wherein the filter bandwidth may be changed. In particular, as described in U.S. Pat. No. 6,178,211, the filter coefficients of a digital signal processor are switchable between a first wideband within a second narrower bandwidth. A post-filter level detector is responsive to the filtered signal and provides a control signal for selecting one of the banks of filter coefficients. Thus, the circuit reduces the effect of adjacent channel interference by narrowing the bandwidth of a filter in the receiver, which reduces the signal content from the adjacent channel propagating through the receiver.
This type of circuit provides an effective method of filtering out of band signals after the ADC. However, gain control in this circuit is based entirely on the signal power present at the input to the ADC, rather, its digital output. This requires an adaptive filtering technique to switch to the proper coefficients as needed. Often, cases arise in which multiple sets of filter coefficients are not available due to signal processing or memory resource restrictions.